§ tb.v

Файл для отладчика icarus verilog testbench.

`timescale 10ns / 1ns
module tb;
// ---------------------------------------------------------------------
reg clock;
reg clock_25;
reg clock_50;

always #0.5 clock    = ~clock;
always #1.0 clock_50 = ~clock_50;
always #1.5 clock_25 = ~clock_25;

initial begin clock = 1; clock_25 = 0; clock_50 = 0; #2000 $finish; end
initial begin $dumpfile("tb.vcd"); $dumpvars(0, tb); end
// ---------------------------------------------------------------------
endmodule

§ Makefile

all:
	iverilog -g2005-sv -DICARUS=1 -o tb.qqq tb.v
	vvp tb.qqq >> /dev/null
vcd:
	gtkwave tb.vcd
wave:
	gtkwave tb.gtkw
clean:
	rm -f *.rpt *.summary *.sof *.done *.pin *.qws *.bak *.smsg *.qws *.vcd \
		  *.qqq *.jic *.map *.qqq undo_redo.txt PLLJ_PLLSPE_INFO.txt
	rm -rf db incremental_db simulation timing output_files

§ .gitignore

*.qqq
*.vcd

§ Модуль памяти

reg  [ 7:0] fb[65536]; // 64к тестовой памяти
wire [ 7:0] data_o = fb[address]; // Читаемые данные
wire [ 7:0] data_i;    // Данные на запись
wire [15:0] address;   // Адрес
wire        data_w;    // Сигнал записи

always @(posedge clock) if (data_w) fb[address] <= data_i;
initial $readmemh("memory.hex", fb, 16'h0000);

§ Простейший шаблон CPU 8 bit

Верхний уровень

cpu UnitCpu
(
    .clock   (clock_25),
    .address (address),
    .data_o  (data_i),
    .data_i  (data_o),
    .data_w  (data_w)
);

Процессор

module cpu(

    input wire          clock,
    output reg [15:0]   address,
    input wire [ 7:0]   data_i,
    output reg [ 7:0]   data_o,
    output reg          data_w
);

initial begin address = 16'h00; data_o = 8'h0; data_w = 1'b1; end

always @(posedge clock) begin
   // code there
end

endmodule