§ Общий шаблон
1`timescale 10ns / 1ns
2module tb;
3
4reg clock, clock_25, clock_50;
5
6always #0.5 clock = ~clock;
7always #1.0 clock_50 = ~clock_50;
8always #2.0 clock_25 = ~clock_25;
9
10initial begin clock = 1; clock_25 = 0; clock_50 = 0; #2000 $finish; end
11initial begin $dumpfile("tb.vcd"); $dumpvars(0, tb); end
12
13endmodule
§ Контроллер памяти
Гарвардская архитектура.
1
2reg [15:0] progmem[65536];
3reg [ 7:0] memdata[65536];
4
5initial begin $readmemh("tb.hex", progmem, 0); end
6
7wire [15:0] pc;
8wire [15:0] address;
9reg [15:0] ir;
10reg [ 7:0] i_data;
11wire [ 7:0] o_data;
12wire we;
13
14
15
16always @(posedge clock) begin
17
18 i_data <= memdata[ address ];
19 ir <= progmem[ pc ];
20
21 if (we) memdata[ address ] <= o_data;
22
23end