§ Верхний уровень

1pll PLL(
2
3    .clk        (clk),          // Входящие 100 Мгц
4    .locked     (locked),       // 1 - готово и стабильно
5    .c0         (clock_25),     // 25,0 Mhz
6    .c1         (clock_12),     // 12,0 Mhz
7    .c2         (clock_6),      //  6,0 Mhz
8    .c3         (clock_50),     // 50,0 Mhz
9);

§ pll.v

1// synopsys translate_off
2`timescale 1 ps / 1 ps
3
4// synopsys translate_on
5module pll (
6    clk,
7    locked,
8    c0, // 25,0 Mhz [1/4]
9    c1, // 12,0 Mhz [3/25]
10    c2, // 6,25 Mhz [1/16]
11    c3  // 50,0 Mhz [1/2]
12);
13
14    input    clk;
15    output   c0;
16    output   c1;
17    output   c2;
18    output   c3;
19    output   locked;
20
21    wire  c0 = clock_wire[0];
22    wire  c1 = clock_wire[1];
23    wire  c2 = clock_wire[2];
24    wire  c3 = clock_wire[3];
25    wire  locked = lck;
26
27    wire [4:0] clock_wire;
28
29    altpll altpll_component (
30        .inclk ({1'h0, clk}),
31        .clk (clock_wire),
32        .activeclock (),
33        .areset (1'b0),
34        .clkbad (),
35        .clkena ({6{1'b1}}),
36        .clkloss (),
37        .clkswitch (1'b0),
38        .configupdate (1'b0),
39        .enable0 (),
40        .enable1 (),
41        .extclk (),
42        .extclkena ({4{1'b1}}),
43        .fbin (1'b1),
44        .fbmimicbidir (),
45        .fbout (),
46        .fref (),
47        .icdrclk (),
48        .locked (lck),
49        .pfdena (1'b1),
50        .phasecounterselect ({4{1'b1}}),
51        .phasedone (),
52        .phasestep (1'b1),
53        .phaseupdown (1'b1),
54        .pllena (1'b1),
55        .scanaclr (1'b0),
56        .scanclk (1'b0),
57        .scanclkena (1'b1),
58        .scandata (1'b0),
59        .scandataout (),
60        .scandone (),
61        .scanread (1'b0),
62        .scanwrite (1'b0),
63        .sclkout0 (),
64        .sclkout1 (),
65        .vcooverrange (),
66        .vcounderrange ()
67    );
68
69defparam
70
71    altpll_component.bandwidth_type = "AUTO",
72
73    // CLOCK 25 Mhz
74    altpll_component.clk0_multiply_by = 1,
75    altpll_component.clk0_divide_by   = 4,
76    altpll_component.clk0_duty_cycle  = 50,
77    altpll_component.clk0_phase_shift = "0",
78
79    // CLOCK 12 Mhz
80    altpll_component.clk1_multiply_by = 3,
81    altpll_component.clk1_divide_by   = 25,
82    altpll_component.clk1_duty_cycle  = 50,
83    altpll_component.clk1_phase_shift = "0",
84
85    // CLOCK 6.25 Mhz
86    altpll_component.clk2_multiply_by = 1,
87    altpll_component.clk2_divide_by   = 16,
88    altpll_component.clk2_duty_cycle  = 50,
89    altpll_component.clk2_phase_shift = "0",
90
91    // CLOCK 50 Mhz
92    altpll_component.clk3_multiply_by = 1,
93    altpll_component.clk3_divide_by   = 2,
94    altpll_component.clk3_duty_cycle  = 50,
95    altpll_component.clk3_phase_shift = "0",
96
97    altpll_component.inclk0_input_frequency = 10000,
98    altpll_component.intended_device_family = "Cyclone III",
99    altpll_component.lpm_type = "altpll",
100    altpll_component.operation_mode = "NO_COMPENSATION",
101    altpll_component.pll_type = "AUTO",
102    altpll_component.port_activeclock = "PORT_UNUSED",
103    altpll_component.port_areset = "PORT_UNUSED",
104    altpll_component.port_clkbad0 = "PORT_UNUSED",
105    altpll_component.port_clkbad1 = "PORT_UNUSED",
106    altpll_component.port_clkloss = "PORT_UNUSED",
107    altpll_component.port_clkswitch = "PORT_UNUSED",
108    altpll_component.port_configupdate = "PORT_UNUSED",
109    altpll_component.port_fbin = "PORT_UNUSED",
110    altpll_component.port_inclk0 = "PORT_USED",
111    altpll_component.port_inclk1 = "PORT_UNUSED",
112    altpll_component.port_locked = "PORT_UNUSED",
113    altpll_component.port_pfdena = "PORT_UNUSED",
114    altpll_component.port_phasecounterselect = "PORT_UNUSED",
115    altpll_component.port_phasedone = "PORT_UNUSED",
116    altpll_component.port_phasestep = "PORT_UNUSED",
117    altpll_component.port_phaseupdown = "PORT_UNUSED",
118    altpll_component.port_pllena    = "PORT_UNUSED",
119    altpll_component.port_scanaclr  = "PORT_UNUSED",
120    altpll_component.port_scanclk   = "PORT_UNUSED",
121    altpll_component.port_scanclkena = "PORT_UNUSED",
122    altpll_component.port_scandata  = "PORT_UNUSED",
123    altpll_component.port_scandataout = "PORT_UNUSED",
124    altpll_component.port_scandone  = "PORT_UNUSED",
125    altpll_component.port_scanread  = "PORT_UNUSED",
126    altpll_component.port_scanwrite = "PORT_UNUSED",
127
128    altpll_component.port_clk0 = "PORT_USED",
129    altpll_component.port_clk1 = "PORT_USED",
130    altpll_component.port_clk2 = "PORT_USED",
131    altpll_component.port_clk3 = "PORT_USED",
132    altpll_component.port_clk4 = "PORT_UNUSED",
133    altpll_component.port_clk5 = "PORT_UNUSED",
134
135    altpll_component.port_clkena0 = "PORT_USED",
136    altpll_component.port_clkena1 = "PORT_USED",
137    altpll_component.port_clkena2 = "PORT_USED",
138    altpll_component.port_clkena3 = "PORT_USED",
139    altpll_component.port_clkena4 = "PORT_UNUSED",
140    altpll_component.port_clkena5 = "PORT_UNUSED",
141
142    altpll_component.port_extclk0 = "PORT_UNUSED",
143    altpll_component.port_extclk1 = "PORT_UNUSED",
144    altpll_component.port_extclk2 = "PORT_UNUSED",
145    altpll_component.port_extclk3 = "PORT_UNUSED",
146    altpll_component.width_clock = 5;
147
148endmodule