§ top-модуль
Здесь подключается ядро A-Z80Скачать готовые файлы.
1`timescale 10ns / 1ns 2 3module tb; 4 5reg clock, clock_25, clock_50; 6 7always #0.5 clock = ~clock; 8always #1.0 clock_50 = ~clock_50; 9always #1.5 clock_25 = ~clock_25; 10 11initial begin clock = 0; clock_25 = 0; clock_50 = 0; #3 nRESET = '1; #2000 $finish; end 12initial begin $dumpfile("tb.vcd"); $dumpvars(0, tb); end 13initial begin $readmemh("tb.hex", memory); end 14 15// Обработка памяти 16reg [7:0] memory[65536]; 17 18// Запись в память 19always @(posedge clock) if (nWR == '0 && nRD == '1 && nMREQ == '0) memory[A] <= D; 20 21// ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 22// A-Z80 CPU 23// ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 24 25wire nM1, nMREQ, nIORQ, nRD, nWR, nRFSH, nHALT, nBUSACK; 26 27reg nRESET = '0; 28wire nWAIT = '1; 29wire nINT = '1; 30wire nNMI = '1; 31wire nBUSRQ = '1; 32 33wire [15:0] A; 34wire [ 7:0] D = nMREQ ? 8'hZZ : (nRD ? 8'hZZ : memory[A]); 35 36z80_top_direct_n z80_ 37( 38 .CLK (clock_25), 39 .A (A), 40 .D (D), 41 42 // Out 43 .nM1 (nM1), // Выполнение M1-такта 44 .nMREQ (nMREQ), // Запрос чтения из памяти 45 .nIORQ (nIORQ), // Запрос чтения из порта 46 .nRD (nRD), // Чтение 47 .nWR (nWR), // Запись 48 .nRFSH (nRFSH), // Цикл обновления DRAM 49 .nHALT (nHALT), // Процессор остановлен 50 .nBUSACK (nBUSACK), // Запрос обработан 51 52 // In 53 .nWAIT (nWAIT), // Сигнал остановки процессора 54 .nINT (nINT), // Прерывание 55 .nNMI (nNMI), // NMI-прерывание 56 .nRESET (nRESET), // Сброс 57 .nBUSRQ (nBUSRQ) // Запрос шины (временный останов процессора) 58); 59 60endmodule 61 62`include "z80_top_direct_n.v" 63`include "sequencer.v" 64`include "resets.v" 65 66`include "address_mux.v" 67`include "alu.v" 68`include "alu_mux_2.v" 69`include "alu_mux_2z.v" 70`include "alu_mux_3z.v" 71`include "alu_mux_4.v" 72`include "alu_mux_8.v" 73`include "alu_bit_select.v" 74`include "alu_core.v" 75`include "alu_control.v" 76`include "alu_flags.v" 77`include "alu_select.v" 78`include "alu_prep_daa.v" 79`include "alu_shifter_core.v" 80`include "alu_slice.v" 81`include "inc_dec.v" 82`include "inc_dec_2bit.v" 83 84`include "address_latch.v" 85`include "address_pins.v" 86`include "bus_control.v" 87`include "bus_switch.v" 88`include "clk_delay.v" 89`include "control_pins_n.v" 90`include "data_pins.v" 91`include "data_switch.v" 92`include "data_switch_mask.v" 93`include "decode_state.v" 94`include "execute.v" 95`include "interrupts.v" 96`include "ir.v" 97`include "memory_ifc.v" 98`include "pin_control.v" 99`include "pla_decode.v" 100 101`include "reg_latch.v" 102`include "reg_control.v" 103`include "reg_file.v"
§ makefile
1all: 2 iverilog -g2005-sv -DICARUS=1 -o tb.qqq tb.v -I cpu/toplevel -I cpu/alu -I cpu/bus -I cpu/control -I cpu/registers 3 vvp tb.qqq >> /dev/null 4vcd: 5 gtkwave tb.vcd 6wave: 7 gtkwave tb.gtkw 8clean: 9 rm -f *.rpt *.summary *.sof *.done *.pin *.qws *.bak *.smsg *.qws *.vcd \ 10 *.qqq *.jic *.map *.qqq undo_redo.txt PLLJ_PLLSPE_INFO.txt 11 rm -rf db incremental_db simulation timing output_files
§ tb.gtkw
Для того, чтобы знать где какие сигналы.[*] [*] GTKWave Analyzer v3.3.66 (w)1999-2015 BSI [*] Thu Nov 30 16:28:15 2023 [*] [dumpfile] "tb.vcd" [dumpfile_mtime] "Thu Nov 30 16:02:00 2023" [dumpfile_size] 889839 [savefile] "tb.gtkw" [timestart] 0 [size] 1280 613 [pos] -1 -1 *-7.000000 135 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 [treeopen] tb. [sst_width] 319 [signals_width] 145 [sst_expanded] 1 [sst_vpaned_height] 160 @28 tb.clock [color] 2 tb.clock_25 @800200 -MEMORY @22 tb.A[15:0] tb.D[7:0] @29 tb.nM1 @28 tb.nRFSH tb.nMREQ tb.nRD tb.nWR @1000200 -MEMORY @800200 -BUS-Out @28 tb.nIORQ tb.nBUSACK tb.nHALT @1000200 -BUS-Out @800200 -BUS-In @28 tb.nRESET tb.nWAIT tb.nINT tb.nNMI tb.nBUSRQ @1000200 -BUS-In [pattern_trace] 1 [pattern_trace] 0