§ tb.v

Файл для отладчика icarus verilog testbench.

1`timescale 10ns / 1ns
2module tb;
3// ---------------------------------------------------------------------
4reg clock;
5reg clock_25;
6reg clock_50;
7
8always #0.5 clock    = ~clock;
9always #1.0 clock_50 = ~clock_50;
10always #2.0 clock_25 = ~clock_25;
11
12initial begin clock = 1; clock_25 = 0; clock_50 = 0; #2000 $finish; end
13initial begin $dumpfile("tb.vcd"); $dumpvars(0, tb); end
14// ---------------------------------------------------------------------
15endmodule

§ Makefile

1all:
2	iverilog -g2005-sv -DICARUS=1 -o tb.qqq tb.v
3	vvp tb.qqq >> /dev/null
4vcd:
5	gtkwave tb.vcd
6wave:
7	gtkwave tb.gtkw
8clean:
9	rm -f *.rpt *.summary *.sof *.done *.pin *.qws *.bak *.smsg *.qws *.vcd \
10		  *.qqq *.jic *.map *.qqq undo_redo.txt PLLJ_PLLSPE_INFO.txt
11	rm -rf db incremental_db simulation timing output_files

§ .gitignore

1*.qqq
2*.vcd

§ Модуль памяти

1reg  [ 7:0] fb[65536]; // 64к тестовой памяти
2wire [ 7:0] data_o = fb[address]; // Читаемые данные
3wire [ 7:0] data_i;    // Данные на запись
4wire [15:0] address;   // Адрес
5wire        data_w;    // Сигнал записи
6
7always @(posedge clock) if (data_w) fb[address] <= data_i;
8initial $readmemh("memory.hex", fb, 16'h0000);

§ Простейший шаблон CPU 8 bit

Верхний уровень

1cpu UnitCpu
2(
3    .clock   (clock_25),
4    .address (address),
5    .data_o  (data_i),
6    .data_i  (data_o),
7    .data_w  (data_w)
8);

Процессор

1module cpu(
2
3    input wire          clock,
4    output reg [15:0]   address,
5    input wire [ 7:0]   data_i,
6    output reg [ 7:0]   data_o,
7    output reg          data_w
8);
9
10initial begin address = 16'h00; data_o = 8'h0; data_w = 1'b1; end
11
12always @(posedge clock) begin
13   // code there
14end
15
16endmodule