§ Общий шаблон tb.v
`timescale 10ns / 1ns
module tb;
reg clock, clock_25, clock_100;
always #0.5 clock_100 = ~clock_100;
always #2.0 clock_25 = ~clock_25;
initial begin clock_100 = 1; clock_25 = 0; #2000 $finish; end
initial begin $dumpfile("tb.vcd"); $dumpvars(0, tb); end
endmodule
§ Makefile
VLIB=/usr/share/verilator/include
all: ica
ica:
iverilog -g2005-sv -DICARUS=1 -o main.qqq tb.v
vvp main.qqq >> /dev/null
vcd:
gtkwave tb.vcd
wav:
gtkwave tb.gtkw
§ Контроллер памяти
Гарвардская архитектура.
reg [15:0] progmem[65536];
reg [ 7:0] memdata[65536];
initial begin $readmemh("tb.hex", progmem, 0); end
wire [15:0] pc;
wire [15:0] address;
reg [15:0] ir;
reg [ 7:0] i_data;
wire [ 7:0] o_data;
wire we;
always @(posedge clock) begin
i_data <= memdata[ address ];
ir <= progmem[ pc ];
if (we) memdata[ address ] <= o_data;
end