§ Общий шаблон tb.v

1`timescale 10ns / 1ns
2module tb;
3// ---------------------------------
4reg clock, clock_25, clock_100;
5// ---------------------------------
6always #0.5 clock_100 = ~clock_100;
7always #2.0 clock_25  = ~clock_25;
8// ---------------------------------
9initial begin clock_100 = 1; clock_25 = 0; #2000 $finish; end
10initial begin $dumpfile("tb.vcd"); $dumpvars(0, tb); end
11// ---------------------------------
12endmodule

§ Makefile

1VLIB=/usr/share/verilator/include
2all: ica
3ica:
4	iverilog -g2005-sv -DICARUS=1 -o main.qqq tb.v
5	vvp main.qqq >> /dev/null
6vcd:
7	gtkwave tb.vcd
8wav:
9	gtkwave tb.gtkw

§ Контроллер памяти

1// ---------------------------------------------------------------------
2reg  [15:0] progmem[65536];
3reg  [ 7:0] memdata[65536];
4// ---------------------------------------------------------------------
5initial begin $readmemh("tb.hex", progmem, 0); end
6// ---------------------------------------------------------------------
7wire [15:0] pc;
8wire [15:0] address;
9reg  [15:0] ir;
10reg  [ 7:0] i_data;
11wire [ 7:0] o_data;
12wire        we;
13// ---------------------------------------------------------------------
14
15// Контроллер блочной памяти
16always @(posedge clock) begin
17
18    i_data <= memdata[ address ];
19    ir     <= progmem[ pc      ];
20
21    if (we) memdata[ address ] <= o_data;
22
23end