1
2`timescale 1 ps / 1 ps
3
4
5module pll
6(
7 input inclk0,
8 output c25,
9 output locked
10);
11
12wire [0:0] sub_wire2 = 1'h0;
13wire [4:0] sub_wire3;
14wire sub_wire5;
15wire sub_wire0 = inclk0;
16wire [1:0] sub_wire1 = {sub_wire2, sub_wire0};
17wire [0:0] sub_wire4 = sub_wire3[0:0];
18assign c25 = sub_wire4;
19assign locked = sub_wire5;
20
21altpll altpll_component (
22 .inclk (sub_wire1),
23 .clk (sub_wire3),
24 .locked (sub_wire5),
25 .activeclock (),
26 .areset (1'b0),
27 .clkbad (),
28 .clkena ({6{1'b1}}),
29 .clkloss (),
30 .clkswitch (1'b0),
31 .configupdate (1'b0),
32 .enable0 (),
33 .enable1 (),
34 .extclk (),
35 .extclkena ({4{1'b1}}),
36 .fbin (1'b1),
37 .fbmimicbidir (),
38 .fbout (),
39 .fref (),
40 .icdrclk (),
41 .pfdena (1'b1),
42 .phasecounterselect ({4{1'b1}}),
43 .phasedone (),
44 .phasestep (1'b1),
45 .phaseupdown (1'b1),
46 .pllena (1'b1),
47 .scanaclr (1'b0),
48 .scanclk (1'b0),
49 .scanclkena (1'b1),
50 .scandata (1'b0),
51 .scandataout (),
52 .scandone (),
53 .scanread (1'b0),
54 .scanwrite (1'b0),
55 .sclkout0 (),
56 .sclkout1 (),
57 .vcooverrange (),
58 .vcounderrange ()
59);
60
61defparam
62 altpll_component.bandwidth_type = "AUTO",
63
64
65 altpll_component.clk0_divide_by = 4,
66 altpll_component.clk0_duty_cycle = 50,
67 altpll_component.clk0_multiply_by = 1,
68 altpll_component.clk0_phase_shift = "0",
69
70 altpll_component.compensate_clock = "CLK0",
71 altpll_component.inclk0_input_frequency = 10000,
72 altpll_component.intended_device_family = "MAX 10",
73 altpll_component.lpm_hint = "CBX_MODULE_PREFIX=my_pll",
74 altpll_component.lpm_type = "altpll",
75 altpll_component.operation_mode = "NORMAL",
76 altpll_component.pll_type = "AUTO",
77
78 altpll_component.port_activeclock = "PORT_UNUSED",
79 altpll_component.port_areset = "PORT_UNUSED",
80 altpll_component.port_clkbad0 = "PORT_UNUSED",
81 altpll_component.port_clkbad1 = "PORT_UNUSED",
82 altpll_component.port_clkloss = "PORT_UNUSED",
83 altpll_component.port_clkswitch = "PORT_UNUSED",
84 altpll_component.port_configupdate = "PORT_UNUSED",
85 altpll_component.port_fbin = "PORT_UNUSED",
86 altpll_component.port_inclk0 = "PORT_USED",
87 altpll_component.port_inclk1 = "PORT_UNUSED",
88 altpll_component.port_locked = "PORT_USED",
89 altpll_component.port_pfdena = "PORT_UNUSED",
90 altpll_component.port_phasecounterselect = "PORT_UNUSED",
91 altpll_component.port_phasedone = "PORT_UNUSED",
92 altpll_component.port_phasestep = "PORT_UNUSED",
93 altpll_component.port_phaseupdown = "PORT_UNUSED",
94 altpll_component.port_pllena = "PORT_UNUSED",
95 altpll_component.port_scanaclr = "PORT_UNUSED",
96 altpll_component.port_scanclk = "PORT_UNUSED",
97 altpll_component.port_scanclkena = "PORT_UNUSED",
98 altpll_component.port_scandata = "PORT_UNUSED",
99 altpll_component.port_scandataout = "PORT_UNUSED",
100 altpll_component.port_scandone = "PORT_UNUSED",
101 altpll_component.port_scanread = "PORT_UNUSED",
102 altpll_component.port_scanwrite = "PORT_UNUSED",
103 altpll_component.port_clk0 = "PORT_USED",
104 altpll_component.port_clk1 = "PORT_UNUSED",
105 altpll_component.port_clk2 = "PORT_UNUSED",
106 altpll_component.port_clk3 = "PORT_UNUSED",
107 altpll_component.port_clk4 = "PORT_UNUSED",
108 altpll_component.port_clk5 = "PORT_UNUSED",
109 altpll_component.port_clkena0 = "PORT_UNUSED",
110 altpll_component.port_clkena1 = "PORT_UNUSED",
111 altpll_component.port_clkena2 = "PORT_UNUSED",
112 altpll_component.port_clkena3 = "PORT_UNUSED",
113 altpll_component.port_clkena4 = "PORT_UNUSED",
114 altpll_component.port_clkena5 = "PORT_UNUSED",
115 altpll_component.port_extclk0 = "PORT_UNUSED",
116 altpll_component.port_extclk1 = "PORT_UNUSED",
117 altpll_component.port_extclk2 = "PORT_UNUSED",
118 altpll_component.port_extclk3 = "PORT_UNUSED",
119 altpll_component.self_reset_on_loss_lock = "OFF",
120 altpll_component.width_clock = 5;
121
122endmodule