§ Коды
Исходный код шаблона
скачать тут. В шаблоне есть vendor-файл для UFM.
§ max10.qpf
1QUARTUS_VERSION = "15.1"
2DATE = "20:37:53 October 03, 2020"
3PROJECT_REVISION = "max10"
§ max10.v
В шаблоне сразу используется модуль UFM.
1module max10(
2
3 output wire [13:0] IO,
4 output wire [ 3:0] LED,
5 input wire KEY0,
6 input wire KEY1,
7 input wire SERIAL_RX,
8 output wire SERIAL_TX,
9 input wire CLK100MHZ
10);
11
12wire drclk;
13wire arshft;
14wire arclk;
15wire drdout;
16
17
18altera_onchip_flash_block # (
19
20 .DEVICE_FAMILY ("MAX 10"),
21 .PART_NAME ("10M02DCV36C8G"),
22 .IS_DUAL_BOOT ("False"),
23 .IS_ERAM_SKIP ("True"),
24 .IS_COMPRESSED_IMAGE ("False"),
25 .INIT_FILENAME ("demo.mif"),
26 .MIN_VALID_ADDR (0),
27 .MAX_VALID_ADDR (3071),
28 .MIN_UFM_VALID_ADDR (0),
29 .MAX_UFM_VALID_ADDR (3071),
30 .ADDR_RANGE1_END_ADDR (3071),
31 .ADDR_RANGE1_OFFSET (512),
32 .ADDR_RANGE2_OFFSET (0),
33
34 .DEVICE_ID ("02"),
35 .INIT_FILENAME_SIM ("")
36
37
38 ) altera_onchip_flash_block_ (
39
40 .xe_ye (1'b1),
41 .se (1'b1),
42 .arclk (arclk),
43 .arshft (arshft),
44 .ardin ({{22{1'b1}}, 1'b0}),
45 .drclk (drclk),
46 .drshft (drshft),
47 .drdin (1'b0),
48 .nprogram (1'b1),
49 .nerase (1'b1),
50 .nosc_ena (1'b0),
51 .par_en (1'b1),
52 .drdout (drdout),
53 .busy (),
54 .se_pass (),
55 .sp_pass (),
56 .osc ()
57 );
58
59endmodule
§ max10.qsf
1set_global_assignment -name FAMILY "MAX 10"
2set_global_assignment -name DEVICE 10M02DCV36C8G
3set_global_assignment -name TOP_LEVEL_ENTITY max10
4set_global_assignment -name ORIGINAL_QUARTUS_VERSION 15.1.0
5set_global_assignment -name PROJECT_CREATION_TIME_DATE "20:37:53 OCTOBER 03, 2020"
6set_global_assignment -name LAST_QUARTUS_VERSION 15.1.0
7set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
8set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
9set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
10set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 256
11set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (Verilog)"
12set_global_assignment -name EDA_OUTPUT_DATA_FORMAT "VERILOG HDL" -section_id eda_simulation
13set_global_assignment -name VERILOG_FILE max10.v
14set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "2.5 V"
15set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
16set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
17set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
18
19set_location_assignment PIN_B6 -to IO[10]
20set_location_assignment PIN_C5 -to IO[11]
21set_location_assignment PIN_C6 -to IO[8]
22set_location_assignment PIN_D6 -to IO[9]
23set_location_assignment PIN_D5 -to IO[6]
24set_location_assignment PIN_E6 -to IO[7]
25set_location_assignment PIN_E5 -to IO[4]
26set_location_assignment PIN_F4 -to IO[2]
27set_location_assignment PIN_E4 -to IO[5]
28set_location_assignment PIN_F3 -to IO[3]
29set_location_assignment PIN_E3 -to IO[1]
30set_location_assignment PIN_F2 -to IO[0]
31set_location_assignment PIN_B2 -to LED[0]
32set_location_assignment PIN_A2 -to LED[1]
33set_location_assignment PIN_A3 -to LED[2]
34set_location_assignment PIN_A4 -to KEY1
35set_location_assignment PIN_E2 -to KEY0
36set_location_assignment PIN_B4 -to LED[3]
37set_location_assignment PIN_A5 -to IO[12]
38set_location_assignment PIN_B5 -to IO[13]
39set_location_assignment PIN_E1 -to SERIAL_RX
40set_location_assignment PIN_D1 -to CLK100MHZ
41set_location_assignment PIN_C2 -to SERIAL_TX
42set_instance_assignment -name IO_STANDARD "2.5 V SCHMITT TRIGGER" -to KEY0
43set_instance_assignment -name IO_STANDARD "2.5 V SCHMITT TRIGGER" -to KEY1
44set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to KEY0
45set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to KEY1
46
47set_global_assignment -name ENABLE_OCT_DONE OFF
48set_global_assignment -name ENABLE_CONFIGURATION_PINS OFF
49set_global_assignment -name ENABLE_BOOT_SEL_PIN OFF
50set_global_assignment -name USE_CONFIGURATION_DEVICE ON
51set_global_assignment -name CRC_ERROR_OPEN_DRAIN OFF
52set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -rise
53set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -fall
54set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -rise
55set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fall
56set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top