§ В чем интерес
Сегодня я попробую сконвертировать код Verilog на JS и проверить, что из этого получится.
§ Исходный код на верилоге
1module vga
2(
3 input clock,
4 output [1:0] r,
5 output [1:0] g,
6 output [1:0] b,
7 output hs,
8 output vs,
9 output reg [12:0] address,
10 input [ 7:0] data,
11 input [10:0] cursor
12);
13
14reg [9:0] x = 10'b0;
15reg [8:0] y = 9'b0;
16
17
18reg flash = 1'b0;
19reg [ 3:0] ticker = 1'b1;
20
21
22reg [7:0] rmask;
23reg [7:0] rcolor;
24reg [7:0] tdata;
25
26wire xborder = x == 10'd799;
27wire yborder = y == 9'd448;
28wire visible = x >= 48 && x < 48+640 && y >= 35 && y <= 35+400;
29
30
31assign hs = x < 48+640+16;
32assign vs = y >= 35+400+12;
33
34
35wire [9:0] xv = x - 40;
36wire [8:0] yv = y - 35;
37
38
39wire pix = rmask[ ~xv[2:0] ];
40
41
42wire enfore = ~(flash & rcolor[7]);
43
44
45wire [10:0] cplace = yv[8:4]*80 + xv[9:3];
46wire acursor = (cursor + 1 == cplace) & (yv[3:0] >= 4'hE);
47
48
49wire [ 3:0] curcolor = (pix & enfore) | (acursor & flash) ? rcolor[3:0] : rcolor[6:4];
50wire [ 5:0] outcolor =
51
52 curcolor == 4'h0 ? 6'b00_00_00 :
53 curcolor == 4'h1 ? 6'b00_00_01 :
54 curcolor == 4'h2 ? 6'b00_01_00 :
55 curcolor == 4'h3 ? 6'b00_01_01 :
56 curcolor == 4'h4 ? 6'b01_00_00 :
57 curcolor == 4'h5 ? 6'b01_00_01 :
58 curcolor == 4'h6 ? 6'b01_01_00 :
59 curcolor == 4'h7 ? 6'b10_10_10 :
60 curcolor == 4'h8 ? 6'b01_01_01 :
61 curcolor == 4'h9 ? 6'b00_00_11 :
62 curcolor == 4'hA ? 6'b00_11_00 :
63 curcolor == 4'hB ? 6'b00_11_11 :
64 curcolor == 4'hC ? 6'b11_00_00 :
65 curcolor == 4'hD ? 6'b11_00_11 :
66 curcolor == 4'hE ? 6'b11_11_00 :
67 6'b11_11_11;
68
69assign {r, g, b} = visible ? outcolor : 6'b00_00_00;
70
71always @(posedge clock) begin
72
73 x <= xborder ? 1'b0 : x + 1'b1;
74 y <= xborder && yborder ? 1'b0 : (xborder ? y + 1'b1 : y);
75
76
77 case (xv[2:0])
78
79
80 3'h0: begin address <= {cplace, 1'b0}; end
81
82 3'h1: begin address[0] <= 1'b1; tdata <= data; end
83
84 3'h2: begin address <= {1'b1, tdata, yv[3:0]}; tdata <= data; end
85
86 3'h7: begin rmask <= data; rcolor <= tdata; end
87
88 endcase
89
90 if (xborder && yborder) begin
91
92 ticker <= ticker + 1'b1;
93 flash <= ticker ? flash : ~flash;
94
95 end
96
97end
98
99endmodule