§ top-модуль
Здесь подключается ядро A-Z80Скачать готовые файлы.
`timescale 10ns / 1ns module tb; reg clock, clock_25, clock_50; always #0.5 clock = ~clock; always #1.0 clock_50 = ~clock_50; always #1.5 clock_25 = ~clock_25; initial begin clock = 0; clock_25 = 0; clock_50 = 0; #3 nRESET = '1; #2000 $finish; end initial begin $dumpfile("tb.vcd"); $dumpvars(0, tb); end initial begin $readmemh("tb.hex", memory); end // Обработка памяти reg [7:0] memory[65536]; // Запись в память always @(posedge clock) if (nWR == '0 && nRD == '1 && nMREQ == '0) memory[A] <= D; // ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ // A-Z80 CPU // ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ wire nM1, nMREQ, nIORQ, nRD, nWR, nRFSH, nHALT, nBUSACK; reg nRESET = '0; wire nWAIT = '1; wire nINT = '1; wire nNMI = '1; wire nBUSRQ = '1; wire [15:0] A; wire [ 7:0] D = nMREQ ? 8'hZZ : (nRD ? 8'hZZ : memory[A]); z80_top_direct_n z80_ ( .CLK (clock_25), .A (A), .D (D), // Out .nM1 (nM1), // Выполнение M1-такта .nMREQ (nMREQ), // Запрос чтения из памяти .nIORQ (nIORQ), // Запрос чтения из порта .nRD (nRD), // Чтение .nWR (nWR), // Запись .nRFSH (nRFSH), // Цикл обновления DRAM .nHALT (nHALT), // Процессор остановлен .nBUSACK (nBUSACK), // Запрос обработан // In .nWAIT (nWAIT), // Сигнал остановки процессора .nINT (nINT), // Прерывание .nNMI (nNMI), // NMI-прерывание .nRESET (nRESET), // Сброс .nBUSRQ (nBUSRQ) // Запрос шины (временный останов процессора) ); endmodule `include "z80_top_direct_n.v" `include "sequencer.v" `include "resets.v" `include "address_mux.v" `include "alu.v" `include "alu_mux_2.v" `include "alu_mux_2z.v" `include "alu_mux_3z.v" `include "alu_mux_4.v" `include "alu_mux_8.v" `include "alu_bit_select.v" `include "alu_core.v" `include "alu_control.v" `include "alu_flags.v" `include "alu_select.v" `include "alu_prep_daa.v" `include "alu_shifter_core.v" `include "alu_slice.v" `include "inc_dec.v" `include "inc_dec_2bit.v" `include "address_latch.v" `include "address_pins.v" `include "bus_control.v" `include "bus_switch.v" `include "clk_delay.v" `include "control_pins_n.v" `include "data_pins.v" `include "data_switch.v" `include "data_switch_mask.v" `include "decode_state.v" `include "execute.v" `include "interrupts.v" `include "ir.v" `include "memory_ifc.v" `include "pin_control.v" `include "pla_decode.v" `include "reg_latch.v" `include "reg_control.v" `include "reg_file.v"
§ makefile
all: iverilog -g2005-sv -DICARUS=1 -o tb.qqq tb.v -I cpu/toplevel -I cpu/alu -I cpu/bus -I cpu/control -I cpu/registers vvp tb.qqq >> /dev/null vcd: gtkwave tb.vcd wave: gtkwave tb.gtkw clean: rm -f *.rpt *.summary *.sof *.done *.pin *.qws *.bak *.smsg *.qws *.vcd \ *.qqq *.jic *.map *.qqq undo_redo.txt PLLJ_PLLSPE_INFO.txt rm -rf db incremental_db simulation timing output_files
§ tb.gtkw
Для того, чтобы знать где какие сигналы.[*] [*] GTKWave Analyzer v3.3.66 (w)1999-2015 BSI [*] Thu Nov 30 16:28:15 2023 [*] [dumpfile] "tb.vcd" [dumpfile_mtime] "Thu Nov 30 16:02:00 2023" [dumpfile_size] 889839 [savefile] "tb.gtkw" [timestart] 0 [size] 1280 613 [pos] -1 -1 *-7.000000 135 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 [treeopen] tb. [sst_width] 319 [signals_width] 145 [sst_expanded] 1 [sst_vpaned_height] 160 @28 tb.clock [color] 2 tb.clock_25 @800200 -MEMORY @22 tb.A[15:0] tb.D[7:0] @29 tb.nM1 @28 tb.nRFSH tb.nMREQ tb.nRD tb.nWR @1000200 -MEMORY @800200 -BUS-Out @28 tb.nIORQ tb.nBUSACK tb.nHALT @1000200 -BUS-Out @800200 -BUS-In @28 tb.nRESET tb.nWAIT tb.nINT tb.nNMI tb.nBUSRQ @1000200 -BUS-In [pattern_trace] 1 [pattern_trace] 0