1module tap
2(
3 input wire reset_n,
4 input wire clock,
5 input wire play,
6 output reg mic,
7 output reg [15:0] tap_address,
8 input wire [7:0] tap_data
9);
10
11`ifdef ICARUS
12parameter
13 PILOT_PERIOD = 4,
14 PILOT_HEADER = 6,
15 PILOT_DATA = 3,
16 SYNC_HI = 4,
17 SYNC_LO = 3,
18 SIGNAL_0 = 2,
19 SIGNAL_1 = 4;
20`else
21parameter
22 PILOT_PERIOD = 2168,
23 PILOT_HEADER = 8064,
24 PILOT_DATA = 3224,
25 SYNC_HI = 667,
26 SYNC_LO = 735,
27 SIGNAL_0 = 855,
28 SIGNAL_1 = 1710;
29`endif
30
31reg [ 3:0] state = 0;
32reg [11:0] cnt = 0;
33reg [12:0] pilot = 0;
34reg [15:0] length = 0;
35reg [10:0] hdata = 0;
36reg [10:0] ldata = 0;
37reg [ 2:0] bitn = 0;
38reg [20:0] delay = 0;
39reg block = 0;
40
41initial tap_address = 0;
42
43always @(posedge clock) begin
44
45 if (!reset_n)
46 begin
47
48 state <= 0;
49 mic <= 1;
50 tap_address <= 0;
51
52 end
53 else case (state)
54
55
56 0: begin state <= play ? 1 : 0; mic <= 1; end
57
58 1: begin state <= 2; length[ 7:0] <= tap_data; tap_address <= tap_address + 1; end
59 2: begin state <= 3; length[15:8] <= tap_data; tap_address <= tap_address + 1; end
60
61 3: begin
62
63 state <= length ? 4 : 15;
64 block <= tap_data[7];
65 pilot <= tap_data[7] ? PILOT_DATA : PILOT_HEADER;
66 delay <= 1750000;
67 bitn <= 7;
68 cnt <= 0;
69
70 end
71
72
73 4: begin
74
75 cnt <= cnt + 1;
76
77
78 if (cnt == PILOT_PERIOD-1)
79 begin
80
81 cnt <= 0;
82 mic <= ~mic;
83 pilot <= pilot - 1;
84
85 if (pilot == 1) begin state <= 5; cnt <= SYNC_HI; end
86
87 end
88
89 end
90
91 5: begin mic <= 1; cnt <= cnt - 1; state <= (cnt == 2) ? 6 : 5; end
92 6: begin mic <= 0; cnt <= cnt + 1; state <= (cnt == SYNC_LO) ? 7 : 6; end
93
94 7: begin
95
96 mic <= 1;
97 bitn <= bitn - 1;
98 state <= 8;
99
100
101 hdata <= tap_data[ bitn ] ? SIGNAL_1 : SIGNAL_0;
102 ldata <= tap_data[ bitn ] ? SIGNAL_1 : SIGNAL_0;
103
104
105
106 if (bitn == 7 && length == 0)
107 state <= (block ? 0 : 10);
108
109
110 if (bitn == 0) begin
111
112 length <= length - 1;
113 tap_address <= tap_address + 1;
114
115 end
116
117 end
118
119
120 8: begin mic <= 1; state <= hdata == 2 ? 9 : 8; hdata <= hdata - 1; end
121 9: begin mic <= 0; state <= ldata == 1 ? 7 : 9; ldata <= ldata - 1; end
122
123
124 10: if (delay) delay <= delay - 1; else state <= 1;
125
126 endcase
127
128end
129
130endmodule